A multi socket non-uniform memory access (NUMA) system includes multiple processor sockets with locally attached memory. In these NUMA multi-socket systems, the system memory is distributed amongst the multiple processor sockets, and each processor socket manages an individual subset (e.g., the locally attached memory) of the overall pool of system memory. A result of the distributed nature of the system memory is that the memories may have a different latency or “temporal cost” to accessing the memory. That is, a processing core within a processor may have lower latency access to the memory that is local to that processor (the memory attached to the processor) as compared to access to memory that is non-local to the processor (e.g., memory attached to a different processor).
Many enterprise applications, such as relational database management systems (RDBMS), are installed on systems having 2 to 4 processor sockets. Demands for increased processing have created a need for applications to scale-up for high count multi-socket systems (e.g., systems having 8, 16, 32, and more processor sockets).
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be used, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein. The aspects of the present disclosure, as generally described herein, and illustrated in the Figures, can be arranged, substituted, combined, separated, and designed in a wide variety of different configurations, all of which are explicitly contemplated herein.